< Back to Blog

Logic Design Engineer


February 13, 2020

Jump to:

Articles you might like

Never miss a Quark!
Sign up for the Newsletter

Subscribe >

    We strongly favor talent and motivation over specific experience. If you are super talented, ready to learn new things, a real team player, and if you believe you have what it takes to face (at least some) of the following challenges – your place is with us.


    • Design and implement a configurable, ultra-low-latency, and highly challenging RTL
    • Ability to learn and understand a full-stack system including SW and HW to for properly implement complex HW-SW interface
    • Pushing the state-of-the-art FPGAs to their limits with regards to logic & timing optimization
    • End2end ownership of the entire coding process (Arch >> uArch >> Design >> Implementation)

    Basic Qualifications

    • Proven track record in RTL coding with System Verilog
    • At least 3 years of experience in chip/FPGA design
    • BSc in Electrical Engineering
    • Knowledge of standard bus protocols (PCIe, DDR, AXI)

    Preferred Qualifications

    • Good understanding of SW/HW interaction
    • Experience in Micro-architecture, Synthesis, and STA
    • Super talented and motivated
    < Back to Blog

    About the Author