Over the next decade, quantum hardware is projected to scale to hundreds of thousands of physical qubits. Yet, a fundamental architectural disconnect persists: bottom-up physical bottlenecks—such as cryogenic payloads and wiring density—are largely treated independently from top-down quantum error correction (QEC) codes. Here, we bridge this divide with a modular, heterogeneous quantum computing architecture that co-designs task-specific hardware tiers with tailored QEC encodings. Our design establishes an explicit microarchitecture featuring fault-tolerant interfaces between quantum processing units (QPUs) and quantum memories, circumventing the scaling limits inherent to monolithic systems. To evaluate this architecture, we introduce an end-to-end resource estimation framework driven by a custom cross-subsystem compiler. Capable of scaling to 1,000 logical qubits, the framework schedules and maps high-level algorithms directly to hardware-native circuit instructions. Comprehensive resource accounting demonstrates orders-of-magnitude reductions in both logical error rates and physical-qubit footprint compared to monolithic surface-code baselines. For 2048-bit RSA factorization mapped to realistic superconducting planar grids, our baseline design executes in 4.9 days using 439k physical qubits. Integrating modular long-range coupling with a qLDPC quantum memory reduces this requirement to 190k qubits in under 10 days, substantially improving upon the space-time efficiency of state-of-the-art fault-tolerant designs.